68302 Software Code Sizes
-------------------------------- 302APPS3 -----------------------------------
| 68302 Software Code Sizes
| _________________________
|
| The software which is supplied by Motorola for the 68302 has
| the following compiled sizes:
| LAPB 20k bytes,
| X.25 36k bytes,
| LAPD 24k bytes,
| Drivers 24k bytes,
| EDX 3k bytes.
|
| The size of the EDX code includes variable and scratch areas
| so this 3k bytes should be resident in RAM. Each of the com-
| munications modules require their own scratch area whose
| size can be calculated with the following equations:
| LAPD $45A + n * $84 bytes, where n = max number of links
| supported,
| LAPB $45A + n * $84 bytes, where n = max number of links
| supported,
| X.25 $46A + n * $84 + m * $14 bytes, where n = max number
| of logical channels to be supported and m = max
| number of DCE/DTE interfaces to be supported.
|
|
68302 Breakpoint Instruction
============================
On page 5-5 of the 68302 User's Manual, a breakpoint instruction cycle
on the address bus is mentioned. The User's Manual is incorrect here;
there is no breakpoint instruction on the 68302.
68302 RMC* Pin
==============
The 302 User's Manual says that RMC* is not negated during an
indivisible cycle. On the 68000 the only instruction that generates an
indivisible cycle where AS* stays low is TAS. BTST is divisible. It is
the same for the RMC* signal on the 302.
Use of 68302 Spare Parameter RAM
================================
When an SCC is not being used, the parameter RAM can be used for general
purpose RAM. The definition of parameter RAM is that part (half) of the
dual port RAM used for parameters and buffer descriptors. Any unused
parameter or buffer descriptor may be freely used if it is not used by
the SCC. The SCC may be disabled or simply not using several of the BDs.
68302 Low Power Wake-Up
=======================
When the 68302 is in the lowest power mode, the EXTAL clock frequency is
externally reduced to less than 8MHz. A 50kHz clock is common. However,
this clock must be brought back into within the specified limits for
EXTAL (8MHz to 16.67MHz) before a wake-up interrupt occurs.
For example, the watchdog timer can be used as a wake|up timer. In this
case the WDOG* signal should be used to force the EXTAL clock back into
the specified range rather than have the watchdog raise an interrupt. If
the clock is not corrected, the 68302 will start to run the reset
routine with an out of specification clock. We then cannot guarantee
exactly how the 68302 will perform at this speed.
68302 DRAM Refresh Controller
=============================
The DRAM refresh controller on the 68302 is a very simple one which is
equivalent to doing a periodic read cycle in software and keeping
software counters and pointers. The SDMA performs one read cycle
whenever it gets a clock on PB8 and it keeps the pointers and counters
internally. This means that the normal 68302/68000 to DRAM logic (RAS
and CAS generation and address multiplexing) must be present but no
extra refresh logic is needed. This logic is totally dependant on the
system being designed so we cannot provide a generic solution.
68302 IDMA and SDMA Function Code Registers
===========================================
At reset the IDMA function code register (FCR) and each SCC's function
code registers (RFCR and TFCR) are undefined. This means that they could
come out of reset as all ones. If the registers are not initialised, the
function code pins will be driven as if an interrupt acknowledge cycle
is occurring whenever the SDMA or IDMA performs a bus cycle. This is not
a desirable situation because the chip select logic will not respond to
an all ones function code. Therefore when initialising the IDMA or SCCs,
you should always write to the function code registers even if the
function codes are not used.
Dynamically changing the 68302 MRBLR
====================================
The maximum length of receive buffers used by the 68302 SCCs is set by
the maximum receive buffer length register, MRBLR, in the parameter RAM
for each SCC. After every buffer is filled, the microcode reads the
MRBLR into the Rx internal byte count. Then it decrements the Rx
internal byte count until it reaches zero. MRBLR can be dynamically
changed but if it is done after the microcode read, another buffer is
received with the previous MRBLR.
68302 UART Fractional Stop Bits
===============================
To clarify the 68302 User's Manual, fractional stop bits are active on
an SCC in UART mode all of the time, regardless of the setting of the SL
bit in the UART mode register. This means that a rev B 68302 can
generate fractional stop bits in the ranges 9/16 to 1 and 1 9/16 to 2.
The SCCs were not designed to support dynamic changes of fractional stop
bits using the DSR.
68302 NMSI Modem Handshake Signals
===================================
The 68302 User's Manual gives the transmit data delays from the CTS* and
RTS* handshaking signals at the beginning of a frame. At the end of a
frame the delay from the last serial bit to RTS* negating is 0 TCLK
periods for async protocols and 1 TCLK period for sync protocols.
If CTS* is negated during transmission of a buffer, there is a delay of
4 TCLK periods for async protocols and 5 TCLK periods for sync protocols
before serial data stops appearing on the TXD pin. RTS* negates at the
same time as CTS*. When CTS* is negated during transmission, the SCC
stops transmission and enters the protocol CTS* lost error procedure.
68302 Transparent Mode Insights
===============================
When an SCC in enabled in promiscuous mode, it cannot recognise a
synchronisation character at the start of a frame. However, it can
synchronise to the falling edge of CD* if the EXSYN bit is set in the
BISYNC node register. Using external hardware, the synchronisation
character can be recognised and CD* asserted which puts the receiver
"in|frame" regardless of the state of CD* until the ENTER HUNT MODE
command is given or an overrun error occurs.
68302 SCC Performance
=====================
The SCC performance ratio tables for the 68302 have been produced for a
two wait state memory system without the DRAM refresh controller turned
off. When the SCP is working there is no effect on the SCC performance.
Each memory wait state has an effect of about 1% on the SCC performance.
The effect of turning on the DRAM refresh controller is dependant on the
refresh period and memory configuration so we cannot give an overall
figure for SCC performance derating.
68302 Multiple PCM Channel Performance
======================================
There are cases when the 68302 is required to receive and transmit on
more than three PCM channels. In this case the envelope method of
synchronising the 68302 to the PCM highway is used and the envelope
covers multiple time slots. If more channels than FIFO length (6 bytes
FIFO = 6 channels) are consecutive then it is the same as supporting one
2 Mbps channel.
For example, if 16 of the 32 channels on a 2Mbps E1 link are to be used,
the average data rate is 1 Mbps. If channels 0, 1, 2, 3 ... 15 are
enveloped then the link should be treated as if it were a 2 Mbps one. If
channels 0, 2, 4, 6 ... 30 are enveloped then the link can be treated as
if it were a 1 Mbps one.
68302 ADS Debug Breakpoints
===========================
If a breakpoint is set to an address and you memory modify this address,
the new value will not be stored. To work around this feature, type:
NOBR address
MM address
BR address.
This anomaly comes about because the breakpoint routine replaces the
word at the specified address with the ILLEGAL instruction and then the
breakpoint is an illegal instruction exception. The memory modify does
not change the breakpoint table which is what is needed.
68302 8-Bit Bus Mode
====================
When using the 8-bit bus mode, data lines D8-D15 are not tri-stated so
they should not be connected to memory devices etc.
68302 Bus Arbitration during Reset
==================================
If BR* is asserted while the 68302 is in reset, BG* will be asserted
straightaway and the requesting device can use the bus and assert BGACK.
When BGACK* is negated, the 68302 will start its reset vector fetch. The
minimum time between BR* asserted and RESET* negating is not specified.
This is the same as the MC68000.
68302 Bus Arbitration during Read Modify Write Cycles
=====================================================
When BR* is asserted during the read part of a read modify write cycle,
output of BG* by the 68302 is delayed until the end of the write cycle.
It would appear that timing spec 35 violated in this case, but what
really happens is spec 64 overrides spec 35 for a read modify write
cycle.
68302 DTACK Generator
=====================
The DTACK generator in the 68302's chip select logic only generates one
long DTACK during a read modify write cycle generated by a TAS
instruction when the RMCST bit in the System Control Register is clear.
In this case, wait states (if selected in the chip select registers) are
only inserted in the read part of the cycle.
When RMCST is set, so that AS* negates between the read and write parts
of the read modify write cycle, two DTACKs are generated each with wait
states inserted in both the read and write cycles.
68302 HDLC Interrupts
=====================
When a buffer is transmitted by the 68302 in HDLC mode, the TXB status
bit in the HDLC Event Register is only set if the I (Interrupt) bit in
the control word of the Tx BD is also set. The corresponding interrupt
can be masked out using the HDLC Mask Register.
If the buffer being transmitted is the last buffer of a frame then TXB,
and it's associated interrupt, is set on transmission of the closing
flag. If the buffer is not the last in a frame then TXB is set after the
buffer's last byte/word is transferred from memory to the transmit FIFO.
68302 HDLC Error Counters
=========================
There is a priority system between the four HDLC error counters, DISFC,
CRCEC, ABTSC and NMARC. ABTSC is only incremented while a frame is being
received and no other conditions are checked. If a frame with an address
match is received but there is a CRC error, only the CRCEC is
incremented. DISFC is only incremented when there are no free receive
buffers and the frames are error free.
68302 HDLC MFLR Parameter
=========================
If an HDLC frame is received which exceeds the 68302 maximum frame
length parameter, held in the MFLR, the remaining data is discarded and
the LG bit is set in the last Rx BD belonging to that frame. The error
condition is reported with the RXF interrupt when the frame ends with
the closing flag, ie. some time after the maximum frame length has been
exceeded.
68302 SCC Performance
=====================
When looking at the 68302 SCC performance ratios, the following should
be remembered:
- When an SCC ENR bit is set and with nothing to receive, there is no
effect on performance,
- When an SCC ENT bit is set and with nothing to transmit, there is a
small effect on performance (the CP has to periodically check the
ready bit in the current Tx BD) .
For example, if three full duplex HDLC channels are running, the serial
performance ratio is 1:37. However, if all three channels have both ENR
and ENT bits set but only one channel is transmitting and receiving (the
others are just idle) then the performance ratio for the one working
channel is a little worse than for one SCC only working. It is slightly
worse because the CP still has to check the ready bits in the Tx BDs of
the two idling channels.
68302 SCC Serial Handshake Lines
================================
When a 68302 SCC is used in NMSI mode, there is delay between the CTS*
or CD* inputs changing state and the RTS* output changing and
transmission/reception starting or stopping. In some applications the
delays, given on page 4-25 of the 68302 User's Manual, are too long. In
this case, the PCM multiplexed mode can be used with the sync signal
enveloping the whole data stream for SCC1. External hardware now drives
the L1SY0 line when both CTS* and CD* are active and there is no delay
before transmission and reception begins or ends. L1SY1 should be held
low.
Using the PCM mode as explained above gives tight control over data flow
but the RTS* signal is lost and must be generated in some other way.
SCC1 is the channel through which data flows in this system can be
configured for any protocol. SCC2 and SCC3 physical interfaces should be
configured in the NMSI mode using the SIMODE register.
There is a problem if more than one serial channel requires very tight
handshake control. Two or three serial channels cannot have this
facility because the serial data to and from all three SCCs needs to be
time division multiplexed onto one serial line in PCM mode.
68302 Profibus Microcode Performance
====================================
The serial performance of an SCC running the Profibus microcode is
similar to the UART mode and the UART performance ratios can be used.
68302 interface with 68881/68882 FPP
====================================
The 68302 can be interfaced to the 68881 or 68882 floating-point co-
processors if the following points are observed :
(1) Timing constraints dictate that for a 16.67MHz 68302, a 20MHz
68881/2 is required, similarly a 20MHz '302 with a 25MHz '881/2.
(2) The 68302 chip selects do not stay active long enough to satisfy
the '881/2 timing specification, and so user chip selects or some
external logic will be required to hold the CS active.
(3) The software required to interface the coprocessor is described
in applications note AN947. As described therein, a subset of
the full capabilities of the coprocessor may be all that is
needed, and as such the functions or macros required may vary
in complexity from application to application. Because of this,
there are no specific performance benchmarks available to us.
68302 ADS Chip Select Registers
===============================
When writing to the 68302 chip select registers using the ADS board, be
careful when selecting areas which are decoded externally for the ADS
boards memory map. In these areas, do not enable DTACK generation. If
you do enable wait state insertion, DTACK* could be generated by the
68302 chip select logic before it is generated by the external DTACK
logic and the memory access completed too early. When fetching program
data from EPROM, invalid data could be read in causing the program to
lock up.
MOTsan Bulletin Board Offers Automatic FAXs of 302 Appnotes
===========================================================
Dave Crumpton in the San Diego office has a bulletin board that he
encourages you and your customers to take advantage of. Besides all the
standard bulletin board functions, it also allows you to fax yourself data
sheets and appnotes of Motorola devices automatically, by selecting items
off a menu. I have already tried it myself and it works great!
The number is (US) 619-279-3907. 8 data, 1 stop, no parity, and up to
2400 baud. The system supports multiple lines, and the probability of a
connection is 86%. There is NO CHARGE for the FAXing feature. You simply
specify the fax number you want the item sent to. All 68302 appnotes and
the new LA data sheet presently exist on the bulletin board.
By the way, the Northeast Bulletin Board at 716-425-2579, is still the
primary location to download 68302 software from, but it will not be
upgraded to have the automatic fax feature that the MOTsan one does.
New Appnote Gives Schematics for a MC68195 LA Board
===================================================
The LocalTalk Adaptor (LA) interfaces the MC68302 to an Appletalk LAN,
or to a proprietary HDLC LAN. This schematic shows how to build a simple
LA board that can be plugged into the ADS302 board, to get started in
developing LA applications. It should be available on the
MOTsan bulletin board.
68302 Training Classes Begin in the States
==========================================
For locations and times of 302 courses, call 800-521-6274. There are
also 302 courses being developed in Europe and Canada. They cover the
68000 core, the System Integration Block, and the Communications
Processor.
68302 Mask Revisions
====================
There has been some confusion about what mask devices belong to which
revision of the functional specification of the 68302. The table below
should clear this up:
Mask Functional Revision
===================================================================
SAMPLE Rev A These were the very first samples shipped.
1B14M Rev A.1 Only a slight change from Rev A devices.
2B14M Rev B First Rev B silicon but not very many shipped.
3B14M Rev B The latest silicon -- still Rev B.
The 68302 Rev 1 Users Manual describes Rev B silicon which contains
some new functions, such as the DRAM refresh controller, which were
not available on the Rev A and A.1 devices.
68302 Internal Vector Fetch
===========================
When the 68302 interrupt controller is providing a vector, the whole
cycle will be seen on the address bus and function control pins and
IAC will be high. For example, if the interrupt controller provides a
level 7 vector, the FC pins will all be high, A1-A3 and A19-A16 are
all high and IAC is high.
68302 Lowest Power Mode
=======================
The following steps give a simple way to enter and exit the lowest
power mode on the 68302:-
1. Set the lower byte of the SCR (location $F7) to $FF.
2. Disable all interrupts except PB11 in the IMR.
3. Turn off any unneeded peripherals, such as the SCCs by clearing
the ENR and ENT bits, and set the Baud Rate Generators to a very
slow rate.
4. Start off a timer to toggle a pin in 20 clocks or so.
5. Execute the STOP instruction.
6. Use the toggled pin to reduce the clock rate to around 50 KHz.
Ensure no glitches occur on the EXTAL signal which exceed the maximum
clock frequency.
7. Power consumption should be lowest now.
8. A wake-up signal comes from the system.
9. Wake-up signal increases the clock frequency to 8-16 MHz and then
pulls PB11 pin low. (Can happen simultaneously if desired).
10. 302 then generates interrupt and 68302 reset is automatically
generated by the low power re-awake logic.
11. 68302 is reset, and s/w processing continues. The 68000 registers
are reset but Dual-port RAM is still intact.
68302 Capacitance De-Rating
===========================
The timing specifications given in the 68302 User's Manual for the
68000 core pins are with a load of 130pF. If the load on these pins is
less, subtract 0.035nS for every pF less than 130pF for 68302 core
pins except CLKO. This rule works down to a load on the pins of 50pF
and these figures are guaranteed by the design of the 68302. The
derating notes given in some of the timing specification tables are
still applicable.
68302 Timing Specification 20
=============================
Timing diagram Figure 6-3 in the 68302 User's Manual shows the end of
the timing spec 20 arrow incorrectly. The description is correct.
68302 Serial Loopback Control
=============================
When all three SCCs on the 68302 are in NMSI mode, they can be
individually put into loopback mode using the DIAG bits in the SCC
mode registers but data will still appear on the TXD pin. In order to
make the TXD2 and TXD3 pins high or low, they should be switched over
to function as output ports. If TXD2 or TXD3 need to be tri-state,
they should be switched over to function as input ports.
The SDIAG bits in the SIMODE register control SCC1 and the other SCCs
only if they are programmed to a multiplexed mode (PCM, IDL or GCI).
Using the SDIAG bits to control loopback tri-states the TXD1 pin and
drives a '1' onto the others when they are programmed to a multiplexed
mode.
68302 Abort Character
=====================
The Abort character is sent out when the stop transmit command is
issued to an SCC in HDLC mode. Whenever the Abort character (7 ones)
is sent out, it is always preceded with a zero. This is useful in the
DMI Mode 3 US ISDN protocol.
68302 FIFO Lengths
==================
The transmit FIFO length is 4 words in HDLC and transparent modes, and
the receive FIFO is 3 words in HDLC and transparent modes. For the
other protocols, substitute bytes instead of words.
68302 Lock Stepping
===================
Some applications of the 68302 require two or more devices to act
synchronously, for example in a fault tolerant system. The 68302 has a
special feature to allow this. If the FRZ* pin of the devices to be
synchronised is pulsed during reset, they will become synchronised
thereafter, even for interrupts and bus arbitration. Unlike the 68020,
there are no internal registers which must be set up by running a
special stream of instructions.
The CP of the 68302 is a microcoded engine so two CPs will stay
synchronised provided they are given the exact same set of stimuli
signals and commands together. Once the two 68302s are in step, all of
inputs signals must meet the setup times (time spec 47 for the core)
but ensure that the signals do not come is too early so that they
could be recognised by one 68302 a cycle before the other.
The microcode's operation is deterministic but it services SCC
requests. The SCC clocks are asynchronous to the core clock so special
attention needs to be given to ensure that SCCs on separate 68302s are
synchronised. When the SCCs are not synchronised the microcode will
not be. Furthermore, the DMA bus cycles depends on the core arbiter
which need to be synchronised. The SCCs and BRGs can be synchronised
when the SCON and SCM registers on both devices are written at the
same time. Take care of external clocks to the SCCs, they are
asynchronous to the parallel clocks and should be within their set up
timing ranges.
Note, this feature is only available on revision B devices and all
devices which are to be synchronised must be of the same mask set.
The following timing for the FRZ* pulse should be used:-
CLKO I--I I--I I--I I--I I--I I--I I--I I--I I--I I--
-I I--I I--I I--I I--I I--I I--I I--I I--I I--I
RESET* and I------
HALT* --------------------------------------------------I
Tsu Th
FRZ* -----------I T1 I----------------------------
I----------------I Td
FRZ* width low (T1) is 2 clocks minimum,
FRZ* set up time to CLKO rising edge (Tsu and spec 205) is 20nS minimum,
FRZ* hold time from CLKO high (Th and spec 206) is 10nS minimum and,
FRZ* high to HALT*/RESET* high (Td) is one clock minimum.
When VCC and the clock, RESET* and HALT* lines are stable FRZ* can go
low.
MC68302 REGISTER REFERENCE
==========================
System Registers Page
---------------- ----
BAR (Base Address Register) 2-15
SCR (System Control Register) 3-48
IDMA Registers
--------------
CMR (Channel Mode Register) 3-3
SAPR (Source Address Pointer Register) 3-7
DAPR (Destination Address Pointer Register) 3-7
FCR (Function Code Register) 3-7
BCR (Byte Count Register) 3-8
CSR (Channel Status Register) 3-8
Interrupt Controller Registers
---------------------------
GIMR (Global Interrupt Mode Register) 3-25
IPR (Interrupt Pending Register) 3-27
IMR (Interrupt Mask Register) 3-27
ISR (Interrupt In-Service Register) 3-28
Parallel I/O Port Registers
------------------------
PACNT (Port A Control Register) 3-32
PADDR (Port A Data Direction Register) 3-32
PADAT (Port A Data Register) 3-32
PBCNT (Port B Control Register) 3-32
PBDDR (Port B Data Direction Register) 3-32
PBDAT (Port B Data Register) 3-32
Timer Registers
---------------
TMR1 (Timer Mode Register 1) 3-37
TMR2 (Timer Mode Register 2) 3-37
TRR1 (Timer Reference Register 1) 3-38
TRR2 (Timer Reference Register 2) 3-38
TCR1 (Timer Capture Register 1) 3-38
TCR2 (Timer Capture Register 2) 3-38
TCN1 (Timer Counter Register 1) 3-38
TCN2 (Timer Counter Register 2) 3-38
TER1 (Timer Event Register 1) 3-39
TER2 (Timer Event Register 2) 3-39
WRR (Watchdog Reference Register) 3-40
WCN (Watchdog Counter Register) 3-41
Chip Select Registers
---------------------
BR0-BR3 (Base Registers) 3-43
OR0-OR3 (Option Registers) 3-45
Communications Processor Registers
----------------------------------
CP (Command Register) 4-4
Serial Interface Registers
--------------------------
SIMODE (Serial Interface Mode Register) 4-16
SIMASK (Serial Interface Mask Register) 4-19
SCC Registers **Generic**
------------------------
SCON (Serial Configuration Registers) 4-22
SCM (SCC Mode Register) 4-25
DSR (Data Synchronization Register) 4-27
BD (Buffer Descriptors) 4-27
SCC Parameter Ram 4-30
TFCR (Transmit Function Code Register) 4-31
RFCR (Receive Function Code Register) 4-31
SCCE (SCC Event Register) 4-34
SCCM (SCC Mask Register) 4-34
SCCS (SCC Status Register) 4-35
SCC Registers (Protocol Specific)
---------------------------------
UART Parameter RAM 4-42
CP (UART commands) 4-43
SCM (UART) 4-51
Rx BD (UART) 4-53
Tx BD (UART) 4-56
SCCE (UART) 4-59
SCCM (UART) 4-60
HDLC Parameter RAM 4-64
CP (HDLC commands) 4-65
SCM (HDLC) 4-69
Rx BD (HDLC) 4-71
Tx BD (HDLC) 4-73
SCCE (HDLC) 4-75
SCCM (HDLC) 4-76
SCP Registers
-------------
SPMODE (SP Mode Register) 4-124
SCP Tx,Rx BD 4-125
Parameter RAM & Register Map 2-17
68302 A0 Timing
===============
The 68302 UDS*/A0 pin functions as A0 in 8-bit bus mode and then has the
same timing specifications as A1-A23.
Things to Check if Your Target Board is not Working
===================================================
1. AVEC* needs to be pulled high if not used, and if used, should be used
in place of DTACK* during the interrupt acknowledge cycle.
2. The Revision B part (2B14M or later) is required for certain features
listed in the REV 1 User's Manual. (Such features include DRAM Refresh,
Asynchronous access by an external master, fractional stop bits in UART,
use of Flow Control feature in UART, FSE bit in HDLC mode, use of BRG1-3
pins, fixed errata in entering DISCPU (slave) mode, VGE bit in disable
CPU mode).
3. Function code registers of IDMA, SDMA or DRAM refresh initialized
to "111", will prevent chip selects from working.
4. Pullup on DTACK* not strong enough. 10K may not be strong enough
in some applications.
5. Pullups omitted from AS*, UDS*, LDS*. 10K will usually do.
6. BR*, FRZ*, BUSW or other inputs left floating will cause problems.
7. 68000 registers A0-A7 or D0-D7 not initialized after reset can cause
intermittant software problems.
8. Watchdog Timer never turned off or refreshed. Can cause a reset if the
WDOG* pin is connected to HALT* and RESET*.
9. Failure to provide the 68K exception table with vectors can cause
erratic behavior when an exception (such as bus error) occurs.
10. When using a protocol, failure to initialize the Parameter RAM will
cause erratic behavior. The two sections of Parameter RAM required to be
initialized are: General Purpose on p. 4-30, and Protocol Specific found in
each protocol section.
11. Chip Select Option Registers not correctly set up as a mask.
Values should be ALL 1's to the left end of the address field, and all 0's
to the right end. Any 0's between the 1's will cause multiple
responses of the CS throughout the address space.
12. IPL lines should be pulled high. 4.7K pullups will work.
13. If the problem is with UART mode, we suggest the app note
"Setting up a UART on the MC68302". One common solution is setting
the MAX_IDL value to 1, instead of 0.
14. If the question is about HDLC mode, suggest the app note
"Buffer Processing and Interrrupt Handling". It uses HDLC as its example.
15. If the question is about IDMA timing, we suggest the app note
"An Overview of the Independent DMA in the MC68302".
16. If the topic is PCM Mode options, or are the customer is
planning to use the PCM mode, reference app note "Using the MC68302
PCM Mode". The app note is an improvement over the manual.
17. For IDL or GCI questions, reference the app notes on these subjects.
18. Look over the User's Manual Errata sheet to see if the problem
is with the REV 1 manual documentation.
19. Look over the" Minimum System Configuration" app note to see if
anything has been left out of their system design.
20. If they have not been able to get interrupts to work yet, we suggest
they try the code in "Getting Started with Interrupts".
21. Don't use bit manipulation instructions to clear the Event registers,
or all bits in that register will be inadvertently cleared. In this mistake
the user calls in and says: "I correctly received data into my SCC receive
buffers, but the 302 did not generate an interrupt to tell me it was there."
The answer was that he accidentally cleared it in his transmit interrupt
service routine by using a bit manipulation instruction.
22. Make sure the stack pointer is initialized to an EVEN address,
otherwise address errors will occur.
23. If the BAR register is written to change both the function code and
the "compare function code" (CFC) bit, make sure that the CFC bit is
written first. This problem often surfaces using a high level language like
C. It may result in a bus error when the software tries to subsequently
access the 68302 peripherals.
24. The BAR register must be written by the program. It does not help for
the EPROM on the target board to have the correct BAR value stored in its
location $F2 (the address of BAR). The BAR register exists on the 302, not
in memory, and must be written with a separate instruction. This problem
often surfaces where the code works on the emulator, but not on the
target.
25. Often, very unusual problems with the SCCs are traced to the fact
that parameter RAM locations in the user source code are not equated with
the proper address. A simple typo in an EQU table can do two things: 1)
cause the parameter RAM value to not be initialized, and 2) cause another
parameter RAM location to be written with the wrong value. This can
make for very unusual behavior.
26. When using the DRAM refresh unit, be aware of the fact that you
cannot refresh external RAM addresses at locations $0F0-0F8 if a chip
select is used to select the DRAM. This is the reserved area that contains
the BAR and SCR registers. This can be easily fixed by using a different
DRAM refresh starting address, or increment/count pattern.
----------------------End of 302APPS2 --------------------------------------
| 68302 Software Code Sizes
| _________________________
|
| The software which is supplied by Motorola for the 68302 has
| the following compiled sizes:
| LAPB 20k bytes,
| X.25 36k bytes,
| LAPD 24k bytes,
| Drivers 24k bytes,
| EDX 3k bytes.
|
| The size of the EDX code includes variable and scratch areas
| so this 3k bytes should be resident in RAM. Each of the com-
| munications modules require their own scratch area whose
| size can be calculated with the following equations:
| LAPD $45A + n * $84 bytes, where n = max number of links
| supported,
| LAPB $45A + n * $84 bytes, where n = max number of links
| supported,
| X.25 $46A + n * $84 + m * $14 bytes, where n = max number
| of logical channels to be supported and m = max
| number of DCE/DTE interfaces to be supported.
|
|
68302 Breakpoint Instruction
============================
On page 5-5 of the 68302 User's Manual, a breakpoint instruction cycle
on the address bus is mentioned. The User's Manual is incorrect here;
there is no breakpoint instruction on the 68302.
68302 RMC* Pin
==============
The 302 User's Manual says that RMC* is not negated during an
indivisible cycle. On the 68000 the only instruction that generates an
indivisible cycle where AS* stays low is TAS. BTST is divisible. It is
the same for the RMC* signal on the 302.
Use of 68302 Spare Parameter RAM
================================
When an SCC is not being used, the parameter RAM can be used for general
purpose RAM. The definition of parameter RAM is that part (half) of the
dual port RAM used for parameters and buffer descriptors. Any unused
parameter or buffer descriptor may be freely used if it is not used by
the SCC. The SCC may be disabled or simply not using several of the BDs.
68302 Low Power Wake-Up
=======================
When the 68302 is in the lowest power mode, the EXTAL clock frequency is
externally reduced to less than 8MHz. A 50kHz clock is common. However,
this clock must be brought back into within the specified limits for
EXTAL (8MHz to 16.67MHz) before a wake-up interrupt occurs.
For example, the watchdog timer can be used as a wake|up timer. In this
case the WDOG* signal should be used to force the EXTAL clock back into
the specified range rather than have the watchdog raise an interrupt. If
the clock is not corrected, the 68302 will start to run the reset
routine with an out of specification clock. We then cannot guarantee
exactly how the 68302 will perform at this speed.
68302 DRAM Refresh Controller
=============================
The DRAM refresh controller on the 68302 is a very simple one which is
equivalent to doing a periodic read cycle in software and keeping
software counters and pointers. The SDMA performs one read cycle
whenever it gets a clock on PB8 and it keeps the pointers and counters
internally. This means that the normal 68302/68000 to DRAM logic (RAS
and CAS generation and address multiplexing) must be present but no
extra refresh logic is needed. This logic is totally dependant on the
system being designed so we cannot provide a generic solution.
68302 IDMA and SDMA Function Code Registers
===========================================
At reset the IDMA function code register (FCR) and each SCC's function
code registers (RFCR and TFCR) are undefined. This means that they could
come out of reset as all ones. If the registers are not initialised, the
function code pins will be driven as if an interrupt acknowledge cycle
is occurring whenever the SDMA or IDMA performs a bus cycle. This is not
a desirable situation because the chip select logic will not respond to
an all ones function code. Therefore when initialising the IDMA or SCCs,
you should always write to the function code registers even if the
function codes are not used.
Dynamically changing the 68302 MRBLR
====================================
The maximum length of receive buffers used by the 68302 SCCs is set by
the maximum receive buffer length register, MRBLR, in the parameter RAM
for each SCC. After every buffer is filled, the microcode reads the
MRBLR into the Rx internal byte count. Then it decrements the Rx
internal byte count until it reaches zero. MRBLR can be dynamically
changed but if it is done after the microcode read, another buffer is
received with the previous MRBLR.
68302 UART Fractional Stop Bits
===============================
To clarify the 68302 User's Manual, fractional stop bits are active on
an SCC in UART mode all of the time, regardless of the setting of the SL
bit in the UART mode register. This means that a rev B 68302 can
generate fractional stop bits in the ranges 9/16 to 1 and 1 9/16 to 2.
The SCCs were not designed to support dynamic changes of fractional stop
bits using the DSR.
68302 NMSI Modem Handshake Signals
===================================
The 68302 User's Manual gives the transmit data delays from the CTS* and
RTS* handshaking signals at the beginning of a frame. At the end of a
frame the delay from the last serial bit to RTS* negating is 0 TCLK
periods for async protocols and 1 TCLK period for sync protocols.
If CTS* is negated during transmission of a buffer, there is a delay of
4 TCLK periods for async protocols and 5 TCLK periods for sync protocols
before serial data stops appearing on the TXD pin. RTS* negates at the
same time as CTS*. When CTS* is negated during transmission, the SCC
stops transmission and enters the protocol CTS* lost error procedure.
68302 Transparent Mode Insights
===============================
When an SCC in enabled in promiscuous mode, it cannot recognise a
synchronisation character at the start of a frame. However, it can
synchronise to the falling edge of CD* if the EXSYN bit is set in the
BISYNC node register. Using external hardware, the synchronisation
character can be recognised and CD* asserted which puts the receiver
"in|frame" regardless of the state of CD* until the ENTER HUNT MODE
command is given or an overrun error occurs.
68302 SCC Performance
=====================
The SCC performance ratio tables for the 68302 have been produced for a
two wait state memory system without the DRAM refresh controller turned
off. When the SCP is working there is no effect on the SCC performance.
Each memory wait state has an effect of about 1% on the SCC performance.
The effect of turning on the DRAM refresh controller is dependant on the
refresh period and memory configuration so we cannot give an overall
figure for SCC performance derating.
68302 Multiple PCM Channel Performance
======================================
There are cases when the 68302 is required to receive and transmit on
more than three PCM channels. In this case the envelope method of
synchronising the 68302 to the PCM highway is used and the envelope
covers multiple time slots. If more channels than FIFO length (6 bytes
FIFO = 6 channels) are consecutive then it is the same as supporting one
2 Mbps channel.
For example, if 16 of the 32 channels on a 2Mbps E1 link are to be used,
the average data rate is 1 Mbps. If channels 0, 1, 2, 3 ... 15 are
enveloped then the link should be treated as if it were a 2 Mbps one. If
channels 0, 2, 4, 6 ... 30 are enveloped then the link can be treated as
if it were a 1 Mbps one.
68302 ADS Debug Breakpoints
===========================
If a breakpoint is set to an address and you memory modify this address,
the new value will not be stored. To work around this feature, type:
NOBR address
MM address
BR address.
This anomaly comes about because the breakpoint routine replaces the
word at the specified address with the ILLEGAL instruction and then the
breakpoint is an illegal instruction exception. The memory modify does
not change the breakpoint table which is what is needed.
68302 8-Bit Bus Mode
====================
When using the 8-bit bus mode, data lines D8-D15 are not tri-stated so
they should not be connected to memory devices etc.
68302 Bus Arbitration during Reset
==================================
If BR* is asserted while the 68302 is in reset, BG* will be asserted
straightaway and the requesting device can use the bus and assert BGACK.
When BGACK* is negated, the 68302 will start its reset vector fetch. The
minimum time between BR* asserted and RESET* negating is not specified.
This is the same as the MC68000.
68302 Bus Arbitration during Read Modify Write Cycles
=====================================================
When BR* is asserted during the read part of a read modify write cycle,
output of BG* by the 68302 is delayed until the end of the write cycle.
It would appear that timing spec 35 violated in this case, but what
really happens is spec 64 overrides spec 35 for a read modify write
cycle.
68302 DTACK Generator
=====================
The DTACK generator in the 68302's chip select logic only generates one
long DTACK during a read modify write cycle generated by a TAS
instruction when the RMCST bit in the System Control Register is clear.
In this case, wait states (if selected in the chip select registers) are
only inserted in the read part of the cycle.
When RMCST is set, so that AS* negates between the read and write parts
of the read modify write cycle, two DTACKs are generated each with wait
states inserted in both the read and write cycles.
68302 HDLC Interrupts
=====================
When a buffer is transmitted by the 68302 in HDLC mode, the TXB status
bit in the HDLC Event Register is only set if the I (Interrupt) bit in
the control word of the Tx BD is also set. The corresponding interrupt
can be masked out using the HDLC Mask Register.
If the buffer being transmitted is the last buffer of a frame then TXB,
and it's associated interrupt, is set on transmission of the closing
flag. If the buffer is not the last in a frame then TXB is set after the
buffer's last byte/word is transferred from memory to the transmit FIFO.
68302 HDLC Error Counters
=========================
There is a priority system between the four HDLC error counters, DISFC,
CRCEC, ABTSC and NMARC. ABTSC is only incremented while a frame is being
received and no other conditions are checked. If a frame with an address
match is received but there is a CRC error, only the CRCEC is
incremented. DISFC is only incremented when there are no free receive
buffers and the frames are error free.
68302 HDLC MFLR Parameter
=========================
If an HDLC frame is received which exceeds the 68302 maximum frame
length parameter, held in the MFLR, the remaining data is discarded and
the LG bit is set in the last Rx BD belonging to that frame. The error
condition is reported with the RXF interrupt when the frame ends with
the closing flag, ie. some time after the maximum frame length has been
exceeded.
68302 SCC Performance
=====================
When looking at the 68302 SCC performance ratios, the following should
be remembered:
- When an SCC ENR bit is set and with nothing to receive, there is no
effect on performance,
- When an SCC ENT bit is set and with nothing to transmit, there is a
small effect on performance (the CP has to periodically check the
ready bit in the current Tx BD) .
For example, if three full duplex HDLC channels are running, the serial
performance ratio is 1:37. However, if all three channels have both ENR
and ENT bits set but only one channel is transmitting and receiving (the
others are just idle) then the performance ratio for the one working
channel is a little worse than for one SCC only working. It is slightly
worse because the CP still has to check the ready bits in the Tx BDs of
the two idling channels.
68302 SCC Serial Handshake Lines
================================
When a 68302 SCC is used in NMSI mode, there is delay between the CTS*
or CD* inputs changing state and the RTS* output changing and
transmission/reception starting or stopping. In some applications the
delays, given on page 4-25 of the 68302 User's Manual, are too long. In
this case, the PCM multiplexed mode can be used with the sync signal
enveloping the whole data stream for SCC1. External hardware now drives
the L1SY0 line when both CTS* and CD* are active and there is no delay
before transmission and reception begins or ends. L1SY1 should be held
low.
Using the PCM mode as explained above gives tight control over data flow
but the RTS* signal is lost and must be generated in some other way.
SCC1 is the channel through which data flows in this system can be
configured for any protocol. SCC2 and SCC3 physical interfaces should be
configured in the NMSI mode using the SIMODE register.
There is a problem if more than one serial channel requires very tight
handshake control. Two or three serial channels cannot have this
facility because the serial data to and from all three SCCs needs to be
time division multiplexed onto one serial line in PCM mode.
68302 Profibus Microcode Performance
====================================
The serial performance of an SCC running the Profibus microcode is
similar to the UART mode and the UART performance ratios can be used.
68302 interface with 68881/68882 FPP
====================================
The 68302 can be interfaced to the 68881 or 68882 floating-point co-
processors if the following points are observed :
(1) Timing constraints dictate that for a 16.67MHz 68302, a 20MHz
68881/2 is required, similarly a 20MHz '302 with a 25MHz '881/2.
(2) The 68302 chip selects do not stay active long enough to satisfy
the '881/2 timing specification, and so user chip selects or some
external logic will be required to hold the CS active.
(3) The software required to interface the coprocessor is described
in applications note AN947. As described therein, a subset of
the full capabilities of the coprocessor may be all that is
needed, and as such the functions or macros required may vary
in complexity from application to application. Because of this,
there are no specific performance benchmarks available to us.
68302 ADS Chip Select Registers
===============================
When writing to the 68302 chip select registers using the ADS board, be
careful when selecting areas which are decoded externally for the ADS
boards memory map. In these areas, do not enable DTACK generation. If
you do enable wait state insertion, DTACK* could be generated by the
68302 chip select logic before it is generated by the external DTACK
logic and the memory access completed too early. When fetching program
data from EPROM, invalid data could be read in causing the program to
lock up.
MOTsan Bulletin Board Offers Automatic FAXs of 302 Appnotes
===========================================================
Dave Crumpton in the San Diego office has a bulletin board that he
encourages you and your customers to take advantage of. Besides all the
standard bulletin board functions, it also allows you to fax yourself data
sheets and appnotes of Motorola devices automatically, by selecting items
off a menu. I have already tried it myself and it works great!
The number is (US) 619-279-3907. 8 data, 1 stop, no parity, and up to
2400 baud. The system supports multiple lines, and the probability of a
connection is 86%. There is NO CHARGE for the FAXing feature. You simply
specify the fax number you want the item sent to. All 68302 appnotes and
the new LA data sheet presently exist on the bulletin board.
By the way, the Northeast Bulletin Board at 716-425-2579, is still the
primary location to download 68302 software from, but it will not be
upgraded to have the automatic fax feature that the MOTsan one does.
New Appnote Gives Schematics for a MC68195 LA Board
===================================================
The LocalTalk Adaptor (LA) interfaces the MC68302 to an Appletalk LAN,
or to a proprietary HDLC LAN. This schematic shows how to build a simple
LA board that can be plugged into the ADS302 board, to get started in
developing LA applications. It should be available on the
MOTsan bulletin board.
68302 Training Classes Begin in the States
==========================================
For locations and times of 302 courses, call 800-521-6274. There are
also 302 courses being developed in Europe and Canada. They cover the
68000 core, the System Integration Block, and the Communications
Processor.
68302 Mask Revisions
====================
There has been some confusion about what mask devices belong to which
revision of the functional specification of the 68302. The table below
should clear this up:
Mask Functional Revision
===================================================================
SAMPLE Rev A These were the very first samples shipped.
1B14M Rev A.1 Only a slight change from Rev A devices.
2B14M Rev B First Rev B silicon but not very many shipped.
3B14M Rev B The latest silicon -- still Rev B.
The 68302 Rev 1 Users Manual describes Rev B silicon which contains
some new functions, such as the DRAM refresh controller, which were
not available on the Rev A and A.1 devices.
68302 Internal Vector Fetch
===========================
When the 68302 interrupt controller is providing a vector, the whole
cycle will be seen on the address bus and function control pins and
IAC will be high. For example, if the interrupt controller provides a
level 7 vector, the FC pins will all be high, A1-A3 and A19-A16 are
all high and IAC is high.
68302 Lowest Power Mode
=======================
The following steps give a simple way to enter and exit the lowest
power mode on the 68302:-
1. Set the lower byte of the SCR (location $F7) to $FF.
2. Disable all interrupts except PB11 in the IMR.
3. Turn off any unneeded peripherals, such as the SCCs by clearing
the ENR and ENT bits, and set the Baud Rate Generators to a very
slow rate.
4. Start off a timer to toggle a pin in 20 clocks or so.
5. Execute the STOP instruction.
6. Use the toggled pin to reduce the clock rate to around 50 KHz.
Ensure no glitches occur on the EXTAL signal which exceed the maximum
clock frequency.
7. Power consumption should be lowest now.
8. A wake-up signal comes from the system.
9. Wake-up signal increases the clock frequency to 8-16 MHz and then
pulls PB11 pin low. (Can happen simultaneously if desired).
10. 302 then generates interrupt and 68302 reset is automatically
generated by the low power re-awake logic.
11. 68302 is reset, and s/w processing continues. The 68000 registers
are reset but Dual-port RAM is still intact.
68302 Capacitance De-Rating
===========================
The timing specifications given in the 68302 User's Manual for the
68000 core pins are with a load of 130pF. If the load on these pins is
less, subtract 0.035nS for every pF less than 130pF for 68302 core
pins except CLKO. This rule works down to a load on the pins of 50pF
and these figures are guaranteed by the design of the 68302. The
derating notes given in some of the timing specification tables are
still applicable.
68302 Timing Specification 20
=============================
Timing diagram Figure 6-3 in the 68302 User's Manual shows the end of
the timing spec 20 arrow incorrectly. The description is correct.
68302 Serial Loopback Control
=============================
When all three SCCs on the 68302 are in NMSI mode, they can be
individually put into loopback mode using the DIAG bits in the SCC
mode registers but data will still appear on the TXD pin. In order to
make the TXD2 and TXD3 pins high or low, they should be switched over
to function as output ports. If TXD2 or TXD3 need to be tri-state,
they should be switched over to function as input ports.
The SDIAG bits in the SIMODE register control SCC1 and the other SCCs
only if they are programmed to a multiplexed mode (PCM, IDL or GCI).
Using the SDIAG bits to control loopback tri-states the TXD1 pin and
drives a '1' onto the others when they are programmed to a multiplexed
mode.
68302 Abort Character
=====================
The Abort character is sent out when the stop transmit command is
issued to an SCC in HDLC mode. Whenever the Abort character (7 ones)
is sent out, it is always preceded with a zero. This is useful in the
DMI Mode 3 US ISDN protocol.
68302 FIFO Lengths
==================
The transmit FIFO length is 4 words in HDLC and transparent modes, and
the receive FIFO is 3 words in HDLC and transparent modes. For the
other protocols, substitute bytes instead of words.
68302 Lock Stepping
===================
Some applications of the 68302 require two or more devices to act
synchronously, for example in a fault tolerant system. The 68302 has a
special feature to allow this. If the FRZ* pin of the devices to be
synchronised is pulsed during reset, they will become synchronised
thereafter, even for interrupts and bus arbitration. Unlike the 68020,
there are no internal registers which must be set up by running a
special stream of instructions.
The CP of the 68302 is a microcoded engine so two CPs will stay
synchronised provided they are given the exact same set of stimuli
signals and commands together. Once the two 68302s are in step, all of
inputs signals must meet the setup times (time spec 47 for the core)
but ensure that the signals do not come is too early so that they
could be recognised by one 68302 a cycle before the other.
The microcode's operation is deterministic but it services SCC
requests. The SCC clocks are asynchronous to the core clock so special
attention needs to be given to ensure that SCCs on separate 68302s are
synchronised. When the SCCs are not synchronised the microcode will
not be. Furthermore, the DMA bus cycles depends on the core arbiter
which need to be synchronised. The SCCs and BRGs can be synchronised
when the SCON and SCM registers on both devices are written at the
same time. Take care of external clocks to the SCCs, they are
asynchronous to the parallel clocks and should be within their set up
timing ranges.
Note, this feature is only available on revision B devices and all
devices which are to be synchronised must be of the same mask set.
The following timing for the FRZ* pulse should be used:-
CLKO I--I I--I I--I I--I I--I I--I I--I I--I I--I I--
-I I--I I--I I--I I--I I--I I--I I--I I--I I--I
RESET* and I------
HALT* --------------------------------------------------I
Tsu Th
FRZ* -----------I T1 I----------------------------
I----------------I Td
FRZ* width low (T1) is 2 clocks minimum,
FRZ* set up time to CLKO rising edge (Tsu and spec 205) is 20nS minimum,
FRZ* hold time from CLKO high (Th and spec 206) is 10nS minimum and,
FRZ* high to HALT*/RESET* high (Td) is one clock minimum.
When VCC and the clock, RESET* and HALT* lines are stable FRZ* can go
low.
MC68302 REGISTER REFERENCE
==========================
System Registers Page
---------------- ----
BAR (Base Address Register) 2-15
SCR (System Control Register) 3-48
IDMA Registers
--------------
CMR (Channel Mode Register) 3-3
SAPR (Source Address Pointer Register) 3-7
DAPR (Destination Address Pointer Register) 3-7
FCR (Function Code Register) 3-7
BCR (Byte Count Register) 3-8
CSR (Channel Status Register) 3-8
Interrupt Controller Registers
---------------------------
GIMR (Global Interrupt Mode Register) 3-25
IPR (Interrupt Pending Register) 3-27
IMR (Interrupt Mask Register) 3-27
ISR (Interrupt In-Service Register) 3-28
Parallel I/O Port Registers
------------------------
PACNT (Port A Control Register) 3-32
PADDR (Port A Data Direction Register) 3-32
PADAT (Port A Data Register) 3-32
PBCNT (Port B Control Register) 3-32
PBDDR (Port B Data Direction Register) 3-32
PBDAT (Port B Data Register) 3-32
Timer Registers
---------------
TMR1 (Timer Mode Register 1) 3-37
TMR2 (Timer Mode Register 2) 3-37
TRR1 (Timer Reference Register 1) 3-38
TRR2 (Timer Reference Register 2) 3-38
TCR1 (Timer Capture Register 1) 3-38
TCR2 (Timer Capture Register 2) 3-38
TCN1 (Timer Counter Register 1) 3-38
TCN2 (Timer Counter Register 2) 3-38
TER1 (Timer Event Register 1) 3-39
TER2 (Timer Event Register 2) 3-39
WRR (Watchdog Reference Register) 3-40
WCN (Watchdog Counter Register) 3-41
Chip Select Registers
---------------------
BR0-BR3 (Base Registers) 3-43
OR0-OR3 (Option Registers) 3-45
Communications Processor Registers
----------------------------------
CP (Command Register) 4-4
Serial Interface Registers
--------------------------
SIMODE (Serial Interface Mode Register) 4-16
SIMASK (Serial Interface Mask Register) 4-19
SCC Registers **Generic**
------------------------
SCON (Serial Configuration Registers) 4-22
SCM (SCC Mode Register) 4-25
DSR (Data Synchronization Register) 4-27
BD (Buffer Descriptors) 4-27
SCC Parameter Ram 4-30
TFCR (Transmit Function Code Register) 4-31
RFCR (Receive Function Code Register) 4-31
SCCE (SCC Event Register) 4-34
SCCM (SCC Mask Register) 4-34
SCCS (SCC Status Register) 4-35
SCC Registers (Protocol Specific)
---------------------------------
UART Parameter RAM 4-42
CP (UART commands) 4-43
SCM (UART) 4-51
Rx BD (UART) 4-53
Tx BD (UART) 4-56
SCCE (UART) 4-59
SCCM (UART) 4-60
HDLC Parameter RAM 4-64
CP (HDLC commands) 4-65
SCM (HDLC) 4-69
Rx BD (HDLC) 4-71
Tx BD (HDLC) 4-73
SCCE (HDLC) 4-75
SCCM (HDLC) 4-76
SCP Registers
-------------
SPMODE (SP Mode Register) 4-124
SCP Tx,Rx BD 4-125
Parameter RAM & Register Map 2-17
68302 A0 Timing
===============
The 68302 UDS*/A0 pin functions as A0 in 8-bit bus mode and then has the
same timing specifications as A1-A23.
Things to Check if Your Target Board is not Working
===================================================
1. AVEC* needs to be pulled high if not used, and if used, should be used
in place of DTACK* during the interrupt acknowledge cycle.
2. The Revision B part (2B14M or later) is required for certain features
listed in the REV 1 User's Manual. (Such features include DRAM Refresh,
Asynchronous access by an external master, fractional stop bits in UART,
use of Flow Control feature in UART, FSE bit in HDLC mode, use of BRG1-3
pins, fixed errata in entering DISCPU (slave) mode, VGE bit in disable
CPU mode).
3. Function code registers of IDMA, SDMA or DRAM refresh initialized
to "111", will prevent chip selects from working.
4. Pullup on DTACK* not strong enough. 10K may not be strong enough
in some applications.
5. Pullups omitted from AS*, UDS*, LDS*. 10K will usually do.
6. BR*, FRZ*, BUSW or other inputs left floating will cause problems.
7. 68000 registers A0-A7 or D0-D7 not initialized after reset can cause
intermittant software problems.
8. Watchdog Timer never turned off or refreshed. Can cause a reset if the
WDOG* pin is connected to HALT* and RESET*.
9. Failure to provide the 68K exception table with vectors can cause
erratic behavior when an exception (such as bus error) occurs.
10. When using a protocol, failure to initialize the Parameter RAM will
cause erratic behavior. The two sections of Parameter RAM required to be
initialized are: General Purpose on p. 4-30, and Protocol Specific found in
each protocol section.
11. Chip Select Option Registers not correctly set up as a mask.
Values should be ALL 1's to the left end of the address field, and all 0's
to the right end. Any 0's between the 1's will cause multiple
responses of the CS throughout the address space.
12. IPL lines should be pulled high. 4.7K pullups will work.
13. If the problem is with UART mode, we suggest the app note
"Setting up a UART on the MC68302". One common solution is setting
the MAX_IDL value to 1, instead of 0.
14. If the question is about HDLC mode, suggest the app note
"Buffer Processing and Interrrupt Handling". It uses HDLC as its example.
15. If the question is about IDMA timing, we suggest the app note
"An Overview of the Independent DMA in the MC68302".
16. If the topic is PCM Mode options, or are the customer is
planning to use the PCM mode, reference app note "Using the MC68302
PCM Mode". The app note is an improvement over the manual.
17. For IDL or GCI questions, reference the app notes on these subjects.
18. Look over the User's Manual Errata sheet to see if the problem
is with the REV 1 manual documentation.
19. Look over the" Minimum System Configuration" app note to see if
anything has been left out of their system design.
20. If they have not been able to get interrupts to work yet, we suggest
they try the code in "Getting Started with Interrupts".
21. Don't use bit manipulation instructions to clear the Event registers,
or all bits in that register will be inadvertently cleared. In this mistake
the user calls in and says: "I correctly received data into my SCC receive
buffers, but the 302 did not generate an interrupt to tell me it was there."
The answer was that he accidentally cleared it in his transmit interrupt
service routine by using a bit manipulation instruction.
22. Make sure the stack pointer is initialized to an EVEN address,
otherwise address errors will occur.
23. If the BAR register is written to change both the function code and
the "compare function code" (CFC) bit, make sure that the CFC bit is
written first. This problem often surfaces using a high level language like
C. It may result in a bus error when the software tries to subsequently
access the 68302 peripherals.
24. The BAR register must be written by the program. It does not help for
the EPROM on the target board to have the correct BAR value stored in its
location $F2 (the address of BAR). The BAR register exists on the 302, not
in memory, and must be written with a separate instruction. This problem
often surfaces where the code works on the emulator, but not on the
target.
25. Often, very unusual problems with the SCCs are traced to the fact
that parameter RAM locations in the user source code are not equated with
the proper address. A simple typo in an EQU table can do two things: 1)
cause the parameter RAM value to not be initialized, and 2) cause another
parameter RAM location to be written with the wrong value. This can
make for very unusual behavior.
26. When using the DRAM refresh unit, be aware of the fact that you
cannot refresh external RAM addresses at locations $0F0-0F8 if a chip
select is used to select the DRAM. This is the reserved area that contains
the BAR and SCR registers. This can be easily fixed by using a different
DRAM refresh starting address, or increment/count pattern.
----------------------End of 302APPS2 --------------------------------------
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