ADVANCED DATA RECORDING TECHNOLOGY CONTROLLERS

         ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ

        ÉÉÉ                                                         ÉÉÉ

        ÉÉÉ   ÚÄÄÄ¿ ÚÄÄÄ¿ ÚÄÂÄ¿ ÚÄÄÄ¿    Â     ÚÄ¿  ÚÄÄÄ¿ ÚÄÂÄ¿   ÉÉÉ

        ÉÉÉ   ³     ³   ³ ³ Á ³ ÃÄÄÄÙ ³   ³ þþþ ³ ³ ³ ÃÄ      ³     ÉÉÉ

        ÉÉÉ   ÀÄÄÄÙ ÀÄÄÄÙ Á   Á Á     ÀÄÄÄÙ     Á ÀÄÙ ÀÄÄÄÙ   Á     ÉÉÉ

        ÉÉÉ                                                         ÉÉÉ

        ÉÉÉ     ÚÄÄ¿ ¿ ÚÄÄ¿   ÚÄÄ¿ ÚÄÄ¿ Ú      ¿       ÚÄÄ¿     ÉÉÉ

        ÉÉÉ     ÚÄÄÙ ³   Ä´ Ä   Ä´ ³  ³ ÃÄÄ¿ Ä ³ ÀÄÄÅ ÀÄÄÅ    ³     ÉÉÉ

        ÉÉÉ     ÀÄÄÙ Á ÀÄÄÙ   ÀÄÄÙ ÀÄÄÙ ÀÄÄÙ   Á    Á    Á    Á     ÉÉÉ

        ÉÉÉ                                                         ÉÉÉ

        ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ

                                 Compliments of

                 The  P e r S t o r   S u p p o r t    B o a r d

                               FidoNet  1:102/523

                               AlterNet 7:401/523

Perstor Systems, Inc.                              Ronald W. Fife

         ADVANCED DATA RECORDING TECHNOLOGY CONTROLLERS 

     Perstor Systems,  Inc. manufactures, markets, and sells four 

Advanced  Data Recording Technology (ADRT) Controllers,  known as 

the  Model PS180-8XT,  PS180-8AT,  and PS180-16F operating  at  9 

megabits per second, and Model PS200-16F operating at 10 megabits 

per  second.   In general,  the PS180 models are intended for use 

with  oxide media  having high coercivity,   or with 3  1/2  inch 

Winchester media which is plated.  The PS200 model is recommended 

for   plated  drives  or  drives  with  thin  film  having   high 

performance, RLL approved internal circuitry. 

     As a brief review of the background of controller  interface 

technology, originally in 1980, Seagate Technology introduced the 

first  ST506   5 1/4 form factor Winchester disk  drive  for  the 

small  computer market.   This specification,  which later became 

modified and known as the IEEE 412 specification,  dictated  some 

general  characteristics  about  the interface to the  drive  and 

relied on certain disk drive technology available at the time.  

     Generally at that time,  the magnetic media had a coercivity 

of 300-350 oersted, motor speed tolerance was from 1% to 4%, head 

flying  heights were above 12 microns,  and a significant  degree 

of error existed in the stepper motor positioning.   The  quality 

of  the  recovery  circuit and automatic gain  control  circuitry 

within  the  drive  was not as advanced as it is today  in  1987.  

Therefore,  the interface specification was limited to 5 megabits 

per   second  and  tightly  controlled  as   Modified   Frequency 

Modulation  (MFM).  Incidentally,  MFM is in effect a form of Run 

Length Limited (RLL) encoding that would typically be called  RLL 

1,3.  

     Later,   two   simultaneous  proposals  for  advancing   the 

interface speed were presented:  one by Seagate Technology  known 

as the ST506/412HP specification in 1984, and the other by Maxtor 

Corporation  known  as the ESDI specification.   The  ST506/412HP 

specification  suggested the use of MFM encoding at  10  megabits 

per  second  and  added a recovery microstep  capability  to  the 

positioner   mechanism,   in  the  belief  that   this   recovery 

positioning  was necessary for recovery of the off-track data  at 

the higher data rates. 

     Since the inception of the original ST506 drives,  a  number 

of  changes  occurred in the industry.   The  original  ST506/412 

controller  designs  did  not  utilize  electronic  checking  and 

correction (ECC);  therefore the soft and hard error rates of the 

disk drive needed to be kept at an absolute minimum for the drive 

to be tolerable and usable.   The specification therefore emerged 

for soft error rates at 1 in 10 to the 10th,  and for hard  error 

rates at 1 in 10 to the 12th.    

     The  ESDI  specification  is very similar to  the  ST506/412 

interface  specification.   However, the data recovery circuit is 

located  within the drive in closer proximity to  the  read/write 

circuitry  and therefore is more immune to transient  noise.   In 

this case,  however, the question of suitable product is really a 

system problem.   The finest drive can be reduced to an un-usable 

and unsuitable product at any statistical error rate when coupled 

with  a bad controller design or a failing controller,  and  vice 

versa.  

 

    Significant  improvements in disk drive technology  have  oc-   

curred in the following areas:

- Motor speed tolerance has dropped to 1% or less. 

- Flying  heights are 10-12 microns and becoming lower.  

- Coercivity has moved from 350 oersted to 600 and 700 oersted. 

- Thin film media has become widely available.  

- Positioner accuracy  has improved. 

- Heat dissipation has decreased. 

- Internal  circuitry for the recovery of the recorded signal and 

  digitization of the recorded signal has improved dramatically.  

     Yet, the fundamental ST506/412 specification has not changed 

since  1980.   Therefore the abundant  mass-produced  controllers 

simply  are  unable  to benefit from the  improvements  in  drive 

technology that have occurred.  

     Beginning  in  1985,  a large number of  high  quality  disk 

drives were available from manufacturers such as Seagate, Maxtor, 

Miniscribe,   Newbury  Data,   Fujitsu,  NEC,  and  others  which 

incorporated all of the improvements necessary to raise recording 

and interface rates.  

     The  original ST506/412 5 megabit specification  controllers 

had  typical  512 byte sectors with 17 sectors  per  track.   The 

concept of 1.5 capacity or 7.5 megabit per second RLL controllers 

from Adaptec,  OMTI,  and Western Digital have raised this sector 

count to 26 sectors per track.  

     The  four models  of the PERSTOR 200  Series  are  what  the 

industry has referred to as ARLL,  recording information at 9 and 

10  megabits  per  second and allocating 31 and  34  sectors  per 

track.   They utilize the same ST506/412 interface and drives  as 

have  been  popular and known in the industry.  This ADRT  (ARLL) 

technology is proprietary to Perstor Systems, Inc. 

     These  controllers were introduced in the fall of  1986  and 

have  been installed throughout the world since that time.   They 

were  introduced  after  approximately two years  of  design  and 

validation   testing  in  an  effort  to  raise   the   interface 

specification for the ST506/412 interface, and to make use of the 

improvements in drive technology that have occurred over the past 

few years. 

     The RLL  recording technique was originally developed by IBM 

on  the 3370 drive,  that drive being a soft-sectored  Winchester 

style  drive  used  with  the IBM 4300  series.   It  utilized  a 

specific  code  structure  for the assignment  of  flux  reversal 

patterns  to groups of binary  information.   A group  of  binary 

information  is examined and and encoded into an optimal encoding 

pattern,  rather  than examining one single bit and  recording  a 

simple  clock or data recording method,  which would lead to very 

high flux reversal rates if the recording interface was increased 

in data rate.

     The 3370 relied on a larger ECC word and dictated a  certain 

assignment of the code and data patterns.  The method used in the 

ST506/412 drives and PERSTOR Controllers is specific in an effort 

to assign the high  frequency pattern to the all-zeros condition, 

which  normally  would occur in the sector  preamble.   The  code 

assignment  will yield flux reversal data rates which are  within 

the tolerance of the original ST506/412 data rates (at or below 5 

megabits per second).

     An example of this structure is the all-ones condition.   It 

can  be  noted that at 10 megabits per  second  data  rates,  the 

actual  code rate to the drive will only be 5 megabits (mega flux 

changes)  per second,  yielding a flux reversal rate the same  as 

experienced in MFM at 5 megabits per second.  

     A  problem inherent in the 1.5 capacity controllers is  that 

the  high frequency pattern does not produce a reversal  rate  at 

any time which is less than 200 nanoseconds rising edge to rising 

edge.   The  7  pattern  of  the code sequence  will  produce  an 

exaggerated  time  period of up to 600  nanoseconds  between  the 

rising  edge  of  the  flux reversals  and  encoded  data.   This 

compares  to the worst case MFM rising edge to rising  edge  time 

period of 400 nanoseconds.  

     Operating  at  a  higher recording rate,  as the  PS180  and 

PS200 models do,  the worst case rising edge to rising edge, (the 

high frequency pattern), drops to 168 nanoseconds on the PS180 at 

9  megabits  per second,  or 150 nanoseconds on the PS200  at  10 

megabits  per  second.   The  long  wave 7  pattern  becomes  448 

nanoseconds,  or  400 nanoseconds rising edge to rising edge  for 

the respective models.  

     On  the one hand,  a logical compromise is made at the  high 

frequency end,  but the compromise is within the flux change  per 

inch  rate of current drives.   On the other hand,  the long wave 

side is brought closer to that which would have been expected  by 

the drive designers when patterning it after 5 megabit per second 

MFM.   Further, the time period between pulses remains at the 100 

nanoseconds rate specified by the original ST506 specification.

    There  are many factors which affect these ADRT  controllers.  

The narrower the pulse, the more we are affected by the following 

factors: 

MEDIA RESOLUTION     

These  controllers  are recommended on media that is oxide  media 

having high coercivity in the 600-700 oersted range.  

HEAD WOBBLE     

Head  wobble  must be minimized so that the jitter  of  the  data 

signal is less than or equal to + 20 nanoseconds.

MOTOR SPEED    

Motor  speed  must be less than 1% tolerance and  preferably  .5% 

tolerance.

TIME DOMAIN FILTERS   

The  time  domain filters present in the drive and the  automatic 

gain  control circuitry,  which recover the analog  head  signal, 

should  be  designed  with the time periods  expected  for  these 

controllers in order to achieve optimum results.  

NOISE   

The  noise from the cable system,  and the noise inherent in  the 

controller, the drive, and its power supply must all be reduced.

ONTRACK POSITIIONING   

The  ontrack  positioning must  be equal to or greater  than  the 

current ontrack positioning of the drives that are listed.     

TEMPERATURE RANGE   

The  temperature  range  of  the product should be  held  to  its 

typical  operational  environment rather than  specified  to  the 

extreme  limits  that  might be present in 5 megabit  per  second 

operation.  

     At  9 megabits per second,  the encoded data rate,  or  code 

data rate, becomes 6 megabits (mega flux changes) per second.  At 

10 megabits per second,  the code rate becomes, in its worst case 

mode, 6.6 megabits per second.  

     When we translate these data rates to flux changes per inch, 

in typical 5 1/4 inch media,  we can get an understanding of what 

the  media requirements must be.   At 9 megabits per second,  the 

flux change per inch rate at the outer track will be approximate

ly  6,200  and approximately 10,362 at the inner  track.   At  10 

megabits  per second,  the outer track flux change rate rises  to 

6,900 and the inner track rate rate rises to 11,514.   These flux 

change rates will vary based upon media size, the amount of media 

that  is  actually utilized by the drive manufacturer  and  their 

position, and the rotational rate of the drive.  

     There  is  a  difference  in the  typical  32  bit  computer 

generated  code  probability  for miscorrection and  the  56  bit 

computer generated code utilized in the PERSTOR 200 Series.  In a 

32  bit computer generated code having an 11 bit drop  out  span, 

the  probability of a miscorrection is 1 in 10 to 4th.   Once  an 

error is detected, the probability of correcting it wrong and not 

knowing  about  it  is 1 in 10 to the 4th.   With a 56  bit  code 

having a 22 bit drop out span,  the probability of  miscorrection 

rises to 1 in 10 to the 7th.

     Because  the  flux reversal rate in the worst case mode  has 

risen  above  5 megabits per second,  by  approximately  20%,  we 

should expect a worst case raw error rate of the drive to decline 

and to be approximately 1 in 10 to the 8th or 1 in 10 to the 9th, 

depending  on  the  model number and the characteristics  of  the 

drive.   Typically,  a  56  bit  ECC capability  will  raise  the 

effective system error rate from 1 in 10 to the 8th to 1 in 10 to 

the 25th or greater.  

     Coupling  with  this   must  be  the nature  of  the  re-try 

algorithms,  by applying algorithms that insure that a stable and 

repeatable  ECC has been detected through rotational re-try,  and 

coupling with it techniques to remove the hysteresis error of the 

positioner  during  re-calibration and  re-try  operations.   All 

become  additive in the process of raising the  effective  system 

error  rate  to  values that are equal to or greater  than  those 

experienced  with 5 megabit controllers and equal to  or  greater 

than those specified by the original ST506/412 specification.  

     In  addition,  it  is important that the controller  provide 

sufficient  signal recovery intelligence to reject splinter  type 

pulses  and noise from the interface before the recovery  circuit 

or before the phase lock loop,  and that the phase lock loop  not 

be  of  such a design as to errantly track  signal  jitter.   The 

cumulative   effect   of  tracking  signal  jitter   raises   the 

probability  of  pushing one cell out of one window into  another 

and thereby introducing error.  

     There  are  a  number of other  factors  and  considerations 

in these controller designs, which include the overall subject of 

noise  reduction,  improved re-try and recovery algorithms,  pre-

compensation on the write side, post-compensation on the recovery 

side, etc. 

    Design  validation included approximately 1 year of  testing, 

and  it is an ongoing process to evaluate  temperature  extremes, 

system  reliability,  and  data  reliability.   Tests  have  been 

conducted with most drives from most manufacturers,  new and used 

drives,  over this 1 year period of time.  We did not expect, nor 

did  we design this controller series to operate with all  drives 

ever  manufactured.   The older ST506/412 drives and those drives  

with  low coercivity values and the other factors which  we  have 

discussed  simply do not have the quality required for  use  with 

these ADRT controllers. 

              Copyright 1988 Perstor Systems, Inc. 

7631 East Greenway Road                       Scottsdale, AZ 85260